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table i part number nominal output voltage (v) REF191 2.048 ref192 2.50 ref193 3.00 ref194 4.50 ref195 5.00 ref196 3.30 ref198 4.096 ordering guide temperature package package model range description option 1 ref19xgp C40 c to +85 c 8-lead plastic dip 2 n-8 ref19xes 3 C40 c to +85 c 8-lead soic so-8 ref19xfs 3 C40 c to +85 c 8-lead soic so-8 ref19xgs C40 c to +85 c 8-lead soic so-8 ref19xgru C40 c to +85 c 8-lead tssop ru-8 ref19xgbc +25 c dice notes 1 n = plastic dip, so = small outline, ru = thin shrink small outline. 2 8-lead plastic dip only available in g grade. 3 ref193 and ref196 are available in g grade only. pin configurations a precision micropower, low dropout, voltage references ref19x series 8-lead narrow-body so and tssop (s suffix and ru suffix) tp v s sleep gnd nc nc output tp 1 2 3 4 8 7 6 5 ref19x series top view (not to scale) rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. 8-lead epoxy dip (p suffix) tp v s sleep gnd nc = no connect tp pins are factory test points no user connection nc nc output tp 1 2 3 4 8 7 6 5 ref19x series top view (not to scale) features initial accuracy: 6 2 mv max temperature coefficient: 5 ppm/ c max low supply current: 45 m a max sleep mode: 15 m a max low dropout voltage load regulation: 4 ppm/ma line regulation: 4 ppm/v high output current: 30 ma short circuit protection applications portable instrumentation a-to-d and d-to-a converters smart sensors solar powered applications loop current powered instrumentations general description ref19x series precision bandgap voltage references use a pat- ented temperature drift curvature correction circuit and laser trimming of highly stable thin film resistors to achieve a very low temperature coefficient and a high initial accuracy. the ref19x series are micropower, low dropout voltage (ldv) devices providing a stable output voltage from supplies as low as 100 mv above the output voltage and consuming less than 45 m a of supply current. in sleep mode, which is enabled by applying a low ttl or cmos level to the sleep pin, the output is turned off and supply current is further reduced to less than 15 m a. the ref19x series references are specified over the extended industrial temperature range (C40 c to +85 c) with typical performance specifications over C40 c to +125 c for applica- tions such as automotive. all electrical grades are available in 8-lead soic; the pdip and tssop are only available in the lowest electrical grade. prod- ucts are also available in die form. test pins (tp) the test pins, pin 1 and pin 5, are reserved for in-package zener-zap. to achieve the highest level of accuracy at the out- put, the zener-zapping technique is used to trim the output voltage. since each unit may require a different amount of ad- justment, the resistance value at the test pins will vary widely from pin-to-pin as well as from part-to-part. the user should not make any physical nor electrical connections to pin 1 and pin 5. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999
ref19x series C2C rev. d REF191Cspecifications electrical characteristics parameter symbol condition min typ max units initial accuracy 1 e grade v o i out = 0 ma 2.046 2.048 2.050 v f grade 2.043 2.053 v g grade 2.038 2.058 v line regulation 2 e grade d v o / d v in 3.0 v v s 15 v, i out = 0 ma 2 4 ppm/v f & g grades 4 8 ppm/v load regulation 2 e grade d v o / d v load v s = 5.0 v, 0 i out 30 ma 4 10 ppm/ma f & g grades 6 15 ppm/ma dropout voltage v s C v o v s = 3.15 v, i load = 2 ma 0.95 v v s = 3.3 v, i load = 10 ma 1.25 v v s = 3.6 v, i load = 30 ma 1.55 v long-term stability 3 d v o 1000 hours @ +125 c1.2mv noise voltage e n 0.1 hz to 10 hz 20 m v p-p notes 1 initial accuracy includes temperature hysteresis effect. 2 line and load regulation specifications include the effect of self-heating. 3 long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 5 ppm/ c f grade 5 10 ppm/ c g grade 3 10 25 ppm/ c line regulation 4 e grade d v o / d v in 3.0 v v s 15 v, i out = 0 ma 5 10 ppm/v f & g grades 10 20 ppm/v load regulation 4 e grade d v o / d v load v s = 5.0 v, 0 i out 25 ma 5 15 ppm/ma f & g grades 10 20 ppm/ma dropout voltage v s C v o v s = 3.15 v, i load = 2 ma 0.95 v v s = 3.3 v, i load = 10 ma 1.25 v v s = 3.6 v, i load = 25 ma 1.55 v sleep pin logic high input voltage v h 2.4 v logic high input current i h C8 m a logic low input voltage v l 0.8 v logic low input current i l C8 m a supply current no load 45 m a sleep mode no load 15 m a notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. (@ v s = 3.3 v, t a = +25 8 c unless otherwise noted) (@ v s = 3.3 v, C40 8 c t a +85 8 c unless otherwise noted)
REF191Cspecifications electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 ppm/ c f grade 5 ppm/ c g grade 3 10 ppm/ c line regulation 4 e grade d v o / d v in 3.0 v v s 15 v, i out = 0 ma 10 ppm/v f & g grades 20 ppm/v load regulation 4 e grade d v o / d v load v s = 5.0 v, 0 i out 20 ma 10 ppm/ma f & g grades 20 ppm/ma dropout voltage v s C v o v s = 3.3 v, i load = 10 ma 1.25 v v s = 3.6 v, i load = 20 ma 1.55 v notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. ref19x series rev. d C3C (@ v s = 3.3 v, C40 8 c t a +125 8 c unless otherwise noted)
ref19x series C4C rev. d ref192Cspecifications electrical characteristics parameter symbol condition min typ max units initial accuracy 1 e grade v o i out = 0 ma 2.498 2.500 2.502 v f grade 2.495 2.505 v g grade 2.490 2.510 v line regulation 2 e grade d v o / d v in 3.0 v v s 15 v, i out = 0 ma 2 4 ppm/v f & g grades 4 8 ppm/v load regulation 2 e grade d v o / d v load v s = 5.0 v, 0 i out 30 ma 4 10 ppm/ma f & g grades 6 15 ppm/ma dropout voltage v s C v o v s = 3.5 v, i load = 10 ma 1.00 v v s = 3.9 v, i load = 30 ma 1.40 v long-term stability 3 d v o 1000 hours @ +125 c1.2mv noise voltage e n 0.1 hz to 10 hz 25 m v p-p notes 1 initial accuracy includes temperature hysteresis effect. 2 line and load regulation specifications include the effect of self-heating. 3 long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 5 ppm/ c f grade 5 10 ppm/ c g grade 3 10 25 ppm/ c line regulation 4 e grade d v o / d v in 3.0 v v s 15 v, i out = 0 ma 5 10 ppm/v f & g grades 10 20 ppm/v load regulation 4 e grade d v o / d v load v s = 5.0 v, 0 i out 25 ma 5 15 ppm/ma f & g grades 10 20 ppm/ma dropout voltage v s C v o v s = 3.5 v, i load = 10 ma 1.00 v v s = 4.0 v, i load = 25 ma 1.50 v sleep pin logic high input voltage v h 2.4 v logic high input current i h C8 m a logic low input voltage v l 0.8 v logic low input current i l C8 m a supply current no load 45 m a sleep mode no load 15 m a notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. (@ v s = 3.3 v, t a = +25 8 c unless otherwise noted) (@ v s = 3.3 v, t a = C40 8 c t a +85 8 c unless otherwise noted)
ref192Cspecifications electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 ppm/ c f grade 5 ppm/ c g grade 3 10 ppm/ c line regulation 4 e grade d v o / d v in 3.0 v v s 15 v, i out = 0 ma 10 ppm/v f & g grades 20 ppm/v load regulation 4 e grade d v o / d v load v s = 5.0 v, 0 i out 20 ma 10 ppm/ma f & g grades 20 ppm/ma dropout voltage v s C v o v s = 3.5 v, i load = 10 ma 1.00 v v s = 4.0 v, i load = 20 ma 1.50 v notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. ref19x series C5C rev. d (@ v s = 3.3 v, C40 8 c t a +125 8 c unless otherwise noted) ref193Cspecifications electrical characteristics parameter symbol condition min typ max units initial accuracy 1 g grade v o i out = 0 ma 2.990 3.0 3.010 v line regulation 2 g grades d v o / d v in 3.3 v, v s 15 v, i out = 0 ma 4 8 ppm/v load regulation 2 g grade d v o / d v load v s = 5.0 v, 0 i out 30 ma 6 15 ppm/ma dropout voltage v s C v o v s = 3.8 v, i load = 10 ma 0.80 v v s = 4.0 v, i load = 30 ma 1.00 v long-term stability 3 d v o 1000 hours @ +125 c 1.2 mv noise voltage e n 0.1 hz to 10 hz 30 m v p-p notes 1 initial accuracy includes temperature hysteresis effect. 2 line and load regulation specifications include the effect of self-heating. 3 long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. (@ v s = 3.3 v, t a = +25 8 c unless otherwise noted)
ref19x series C6C rev. d ref193Cspecifications electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 g grade 3 tcv o / ci out = 0 ma 10 25 ppm/ c line regulation 4 g grade d v o / d v in 3.3 v v s 15 v, i out = 0 ma 10 20 ppm/v load regulation 4 g grade d v o / d v load v s = 5.0 v, 0 i out 25 ma 10 20 ppm/ma dropout voltage v s C v o v s = 3.8 v, i load = 10 ma 0.80 v v s = 4.1 v, i load = 30 ma 1.10 v sleep pin logic high input voltage v h 2.4 v logic high input current i h C8 m a logic low input voltage v l 0.8 v logic low input current i l C8 m a supply current no load 45 m a sleep mode no load 15 m a notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 g grade 3 tcv o / ci out = 0 ma 10 ppm/ c line regulation 4 g grade d v o / d v in 3.3 v v s 15 v, i out = 0 ma 20 ppm/v load regulation 4 g grade d v o / d v load v s = 5.0 v, 0 i out 20 ma 10 ppm/ma dropout voltage v s C v o v s = 3.8 v, i load = 10 ma 0.80 v v s = 4.1 v, i load = 20 ma 1.10 v notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. (@ v s = 3.3 v, C40 8 c t a +125 8 c unless otherwise noted) (@ v s = 3.3 v, t a = C40 8 c t a +85 8 c unless otherwise noted)
ref194Cspecifications electrical characteristics parameter symbol condition min typ max units initial accuracy 1 e grade v o i out = 0 ma 4.498 4.5 4.502 v f grade 4.495 4.505 v g grade 4.490 4.510 v line regulation 2 e grade d v o / d v in 4.75 v v s 15 v, i out = 0 ma 2 4 ppm/v f & g grades 4 8 ppm/v load regulation 2 e grade d v o / d v load v s = 5.8 v, 0 i out 30 ma 2 4 ppm/ma f & g grades 4 8 ppm/ma dropout voltage v s C v o v s = 5.00 v, i load = 10 ma 0.50 v v s = 5.8 v, i load = 30 ma 1.30 v long-term stability 3 d v o 1000 hours @ +125 c2mv noise voltage e n 0.1 hz to 10 hz 45 m v p-p notes 1 initial accuracy includes temperature hysteresis effect. 2 line and load regulation specifications include the effect of self-heating. 3 long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 5 ppm/ c f grade 5 10 ppm/ c g grade 3 10 25 ppm/ c line regulation 4 e grade d v o / d v in 4.75 v v s 15 v, i out = 0 ma 5 10 ppm/v f & g grades 10 20 ppm/v load regulation 4 e grade d v o / d v load v s = 5.80 v, 0 i out 25 ma 5 15 ppm/ma f & g grades 10 20 ppm/ma dropout voltage v s C v o v s = 5.00 v, i load = 10 ma 0.5 v v s = 5.80 v, i load = 25 ma 1.30 v sleep pin logic high input voltage v h 2.4 v logic high input current i h C8 m a logic low input voltage v l 0.8 v logic low input current i l C8 m a supply current no load 45 m a sleep mode no load 15 m a notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. ref19x series C7C rev. d (@ v s = 5.0 v, t a = C40 8 c t a +85 8 c unless otherwise noted) (@ v s = 5.0 v, t a = +25 8 c unless otherwise noted)
ref19x series C8C rev. d ref194Cspecifications electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 ppm/ c f grade 5 ppm/ c g grade 3 10 ppm/ c line regulation 4 e grade d v o / d v in 4.75 v v s 15 v, i out = 0 ma 5 ppm/v f & g grades 10 ppm/v load regulation 4 e grade d v o / d v load v s = 5.80 v, 0 i out 20 ma 5 ppm/ma f & g grades 10 ppm/ma dropout voltage v s C v o v s = 5.10 v, i load = 10 ma 0.60 v v s = 5.95 v, i load = 20 ma 1.45 v notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. (@ v s = 5.0 v, C40 8 c t a +125 8 c unless otherwise noted)
ref195Cspecifications electrical characteristics parameter symbol condition min typ max units initial accuracy 1 e grade v o i out = 0 ma 4.998 5.0 5.002 v f grade 4.995 5.005 v g grade 4.990 5.010 v line regulation 2 e grade d v o / d v in 5.10 v v s 15 v, i out = 0 ma 2 4 ppm/v f & g grades 4 8 ppm/v load regulation 2 e grade d v o / d v load v s = 6.30 v, 0 i out 30 ma 2 4 ppm/ma f & g grades 4 8 ppm/ma dropout voltage v s C v o v s = 5.50 v, i load = 10 ma 0.50 v v s = 6.30 v, i load = 30 ma 1.30 v long-term stability 3 d v o 1000 hours @ +125 c1.2mv noise voltage e n 0.1 hz to 10 hz 50 m v p-p notes 1 initial accuracy includes temperature hysteresis effect. 2 line and load regulation specifications include the effect of self-heating. 3 long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 5 ppm/ c f grade 5 10 ppm/ c g grade 3 10 25 ppm/ c line regulation 4 e grade d v o / d v in 5.15 v v s 15 v, i out = 0 ma 5 10 ppm/v f & g grades 10 20 ppm/v load regulation 4 e grade d v o / d v load v s = 6.30 v, 0 i out 25 ma 5 10 ppm/ma f & g grades 10 20 ppm/ma dropout voltage v s C v o v s = 5.50 v, i load = 10 ma 0.50 v v s = 6.30 v, i load = 25 ma 1.30 v sleep pin logic high input voltage v h 2.4 v logic high input current i h C8 m a logic low input voltage v l 0.8 v logic low input current i l C8 m a supply current no load 45 m a sleep mode no load 15 m a notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. . ref19x series rev. d C9C (@ v s = 5.15 v, t a = C40 8 c t a +85 8 c unless otherwise noted) (@ v s = 5.10 v, t a = +25 8 c unless otherwise noted)
ref19x series C10C rev. d ref195Cspecifications electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 ppm/ c f grade 5 ppm/ c g grade 3 10 ppm/ c line regulation 4 e grade d v o / d v in 5.20 v v s 15 v, i out = 0 ma 5 ppm/v f & g grades 10 ppm/v load regulation 4 e grade d v o / d v load v s = 6.45 v, 0 i out 20 ma 5 ppm/ma f & g grades 10 ppm/ma dropout voltage v s C v o v s = 5.60 v, i load = 10 ma 0.60 v v s = 6.45 v, i load = 20 ma 1.45 v notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. ref196Cspecifications electrical characteristics parameter symbol condition min typ max units initial accuracy 1 g grade v o i out = 0 ma 3.290 3.3 3.310 v line regulation 2 g grades d v o / d v in 3.50 v v s 15 v, i out = 0 ma 4 8 ppm/v load regulation 2 g grade d v o / d v load v s = 5.0 v, 0 i out 30 ma 6 15 ppm/ma dropout voltage v s C v o v s = 4.1 v, i load = 10 ma 0.80 v v s = 4.3 v, i load = 30 ma 1.00 v long-term stability 3 d v o 1000 hours @ +125 c1.2mv noise voltage e n 0.1 hz to 10 hz 33 m v p-p notes 1 initial accuracy includes temperature hysteresis effect. 2 line and load regulation specifications include the effect of self-heating. 3 long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. (@ v s = +5.20 v, C40 8 c t a +125 8 c unless otherwise noted) (@ v s = +3.5 v, t a = +25 8 c unless otherwise noted)
ref196Cspecifications electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 g grade 3 tcv o / ci out = 0 ma 10 25 ppm/ c line regulation 4 g grade d v o / d v in 3.5 v v s 15 v, i out = 0 ma 10 20 ppm/v load regulation 4 g grade d v o / d v load v s = 5.0 v, 0 i out 25 ma 10 20 ppm/ma dropout voltage v s C v o v s = 4.1 v, i load = 10 ma 0.80 v v s = 4.3 v, i load = 25 ma 1.00 v sleep pin logic high input voltage v h 2.4 v logic high input current i h C8 m a logic low input voltage v l 0.8 v logic low input current i l C8 m a supply current no load 45 m a sleep mode no load 15 m a notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 g grade 3 tcv o / ci out = 0 ma 10 ppm/ c line regulation 4 g grade d v o / d v in 3.50 v v s 15 v, i out = 0 ma 20 ppm/v load regulation 4 g grade d v o / d v load v s = 5.0 v, 0 i out 20 ma 20 ppm/ma dropout voltage v s C v o v s = 4.1 v, i load = 10 ma 0.80 v v s = 4.4 v, i load = 20 ma 1.10 v notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. ref19x series rev. d C11C (@ v s = +3.50 v, C40 8 c t a +125 8 c unless otherwise noted) (@ v s = +3.5 v, t a = C40 8 c t a +85 8 c unless otherwise noted)
ref19x series C12C rev. d ref198Cspecifications electrical characteristics parameter symbol condition min typ max units initial accuracy 1 e grade v o i out = 0 ma 4.094 4.096 4.098 v f grade 4.091 4.101 v g grade 4.086 4.106 v line regulation 2 e grade d v o / d v in 4.5 v v s 15 v, i out = 0 ma 2 4 ppm/v f & g grades 4 8 ppm/v load regulation 2 e grade d v o / d v load v s = 5.4 v, 0 i out 30 ma 2 4 ppm/ma f & g grades 4 8 ppm/ma dropout voltage v s C v o v s = 4.6 v, i load = 10 ma 0.50 v v s = 5.4 v, i load = 30 ma 1.30 v long-term stability 3 d v o 1000 hours @ +125 c1.2mv noise voltage e n 0.1 hz to 10 hz 40 m v p-p notes 1 initial accuracy includes temperature hysteresis effect. 2 line and load regulation specifications include the effect of self-heating. 3 long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 c, with an ltpd of 1.3. specifications subject to change without notice. electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 5 ppm/ c f grade 5 10 ppm/ c g grade 3 10 25 ppm/ c line regulation 4 e grade d v o / d v in 4.5 v v s 15 v, i out = 0 ma 5 10 ppm/v f & g grades 10 20 ppm/v load regulation 4 e grade d v o / d v load v s = 5.4 v, 0 i out 25 ma 5 10 ppm/ma f & g grades 10 20 ppm/ma dropout voltage v s C v o v s = 4.6 v, i load = 10 ma 0.50 v v s = 5.4 v, i load = 25 ma 1.30 v sleep pin logic high input voltage v h 2.4 v logic high input current i h C8 m a logic low input voltage v l 0.8 v logic low input current i l C8 m a supply current no load 45 m a sleep mode no load 15 m a notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. . (@ v s = 5.0 v, t a = +25 8 c unless otherwise noted) (@ v s = +5.0 v, C40 8 c t a +85 8 c unless otherwise noted)
ref198Cspecifications electrical characteristics parameter symbol condition min typ max units temperature coefficient 1, 2 e grade tcv o / ci out = 0 ma 2 ppm/ c f grade 5 ppm/ c g grade 3 10 ppm/ c line regulation 4 e grade d v o / d v in 4.5 v v s 15 v, i out = 0 ma 5 ppm/v f & g grades 10 ppm/v load regulation 4 e grade d v o / d v load v s = 5.6 v, 0 i out 20 ma 5 ppm/ma f & g grades 10 ppm/ma dropout voltage v s C v o v s = 4.7 v, i load = 10 ma 0.60 v v s = 5.6 v, i load = 20 ma 1.50 v notes 1 for proper operation, a 1 m f capacitor is required between the output pin and the gnd pin of the device. 2 tcv o is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ c. tcv o = ( v maxCv min )/v o ( t max Ct min ). 3 guaranteed by characterization. 4 line and load regulation specifications include the effect of self-heating. specifications subject to change without notice. ref19x series rev. d C13C (@ v s = +5.0 v, C40 8 c t a +125 8 c unless otherwise noted)
ref19x series C14C rev. d wafer test limits parameter symbol condition limits units initial accuracy REF191 v o 2.043/2.053 v ref192 2.495/2.505 v ref193 2.990/3.010 v ref194 4.495/4.505 v ref195 4.995/5.005 v ref196 3.290/3.310 v ref198 4.091/4.101 v line regulation d v o / d v in (v o + 0.5 v) < v in < 15 v, i out = 0 ma 15 ppm/v load regulation d v o / d i load 0 ma < i load < 30 ma, v in = (v o + 1.3 v) 15 ppm/ma dropout voltage v o C v+ i load = 10 ma 1.25 v i load = 30 ma 1.55 v sleep mode input logic input high v ih 2.4 v logic input low v il 0.8 v supply current v in = 15 v no load 45 m a sleep mode no load 15 m a note for proper operation, a 1 m f capacitor is required between the output pins and the gnd pin of the ref19x. electrical tests and wafer probe to the limits s hown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. con sult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +18 v output to gnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v s + 0.3 v output to gnd short-circuit duration . . . . . . . . . . indefinite storage temperature range p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range ref19x . . . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range p, s package . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c package type u ja 2 u jc units 8-lead plastic dip (p) 103 43 c/w 8-lead soic (s) 158 43 c/w 8-lead tssop 240 43 c/w notes 1 absolute maximum rating applies to both dice and packaged parts, unless otherwise noted. 2 q ja is specified for worst case conditions, i.e., q ja is specified for device in socket for p-dip, and q ja is specified for device soldered in circuit board for soic package. dice characteristics output 6 output 6 4 gnd 3 sleep 2 v+ ref19x die size 0.041 0.057 inch, 2,337 sq. mils substrate is connected to v+, number of transistors: bipolar 25, mosfet4. process: cbcmos1 (@ i load = 0 ma, t a = +25 c unless otherwise noted) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ref19x features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. d C15C ref19x series 5.004 4.996 100 4.998 4.997 C25 C50 5.000 4.999 5.001 5.002 5.003 75 50 25 0 temperature C 8 c output voltage C volts 3 typical parts 5.15v < v in < 15v figure 1. ref195 output voltage vs. temperature 32 0 30 8 4 5 0 16 12 20 24 28 25 20 15 10 i load C ma line regulation C ppm/v C40 8 c +25 8 c +5.15v v s 15v +85 8 c figure 2. ref195 line regulation vs. i load 20 0 16 12 4 6 8 4 16 14 12 10 8 v in C volts load regulation C ppm/ma +85 8 c +25 8 c C40 8 c o i out < 25ma figure 3. ref195 load regulation vs. v in 50 0 20 15 5 C15 10 C20 30 20 25 35 40 45 15 10 5 0 C5 C10 t c Cv out C ppm/ 8 c percentage of parts C % C40 8 c t a +85 8 c based on 600 units, 4 runs figure 4. t c C v out distribution 40 0 100 10 5 C25 C50 20 15 25 30 35 75 50 25 0 temperature C 8 c supply current C m a normal mode sleep mode figure 5. quiescent current vs. temperature C6 0 100 C3 C1 C25 C2 C50 C5 C4 75 50 25 0 temperature C 8 c sleep pin current C m a v l v h figure 6. sleep pin current vs. temperature
ref19x series C16C rev. d 10 100 1m 100k 10k 1k C60 C40 C20 0 C120 C100 C80 frequency C hz ripple rejection C db figure 7a. ripple rejection vs. frequency ref19x 6 4 2 1k v ref 10 m f v in = +15v output 1k v 10 m f 1 m f 10 m f figure 7b. ripple rejection vs. frequency measurement circuit 0 10 100 10m 1m 100k 10k 1k 1 2 3 4 frequency C hz v g = 2v p-p v s = 4.00v v in = 7v ref19x 6 4 2 200 v 1 m f z 1 m f i o C v figure 8. output impedance vs. frequency 100 m s 20mv 5v 10 0% 90 on off 100 figure 9a. load transient response v in = 15v 0 10ma 6 ref19x 2 4 1 m f figure 9b. load transient response measurement circuit 10 100 0% 90 2v 2v 1ma load 30ma load 100 m s figure 10a. power on response time v in = 7.0v ref19x 2 4 6 1 m f figure 10b. power on response time measurement circuit 10 100 0% 90 1v 2ms 5v on off v out i l = 1ma i l = 10ma figure 11a. sleep response time v in = 15v ref19x v out 6 2 4 3 1 m f figure 11b. sleep response time measurement circuit
rev. d C17C ref19x series 35 0 0.9 15 5 0.1 10 0 30 20 25 0.8 0.7 0.6 0.5 0.4 0.3 0.2 ref195 dropout voltage C v load current C ma figure 13. dropout voltage vs. load current 10 100 0% 90 5v 200mv 200 m s figure 12. line transient response output voltage bypassing for stable operation, low dropout voltage regulators and refer- ences, in general, require a bypass capacitor connected from their v out pins to their gnd pins. although the ref19x family of references is capable of stable operation with capacitive loads exceeding 100 m f, a 1 m f capacitor is sufficient to guaran- tee rated performance. the addition of a 0.1 m f ceramic ca- pacitor in parallel with the bypass capacitor will improve load current transient performance. for best line voltage transient performance, it is recommended that the voltage inputs of these devices be bypassed with a 10 m f electrolytic capacitor in paral- lel with a 0.1 m f ceramic capacitor. sleep mode operation all ref19x devices include a sleep capability that is ttl/ cmos level compatible. internal to the ref19x at the sleep pin, a pull-up current source to v in is connected. this permits the sleep pin to be driven from an open collector/drain driver. a logic low or a zero volt condition on the sleep pin is re- quired to turn the output stage off. during sleep, the output of the references becomes a high impedance state where its potential would then be determined by external circuitry. if the sleep feature is not used, it is recommended that the sleep pin be connected to v in (pin 2). basic voltage reference connections the circuit in figure 15 illustrates the basic configuration for the ref19x family of references. note the 10 m f/0.1 m f bypass network on the input and the 1 m f/0.1 m f bypass network on the output. it is recommended that no connections be made to pins 1, 5, 7 and 8. if the sleep feature is not required, pin 3 should be connected to v in . nc nc v in sleep 1 2 3 4 8 7 6 5 nc nc 1 m f tant output 0.1 m f 10 m f 0.1 m f ref19x figure 15. basic voltage reference configuration +v v out shutdown gnd figure 14. simplified schematic applications section output short circuit behavior the ref19x family of devices is totally protected from damage due to accidental output shorts to gnd or to v+. in the event of an accidental short circuit condition, the reference device will shutdown and limit its supply current to 100 m a. device power dissipation considerations the ref19x family of references is capable of delivering load currents to 30 ma with an input voltage that ranges from 3.3 v to 15 v. when these devices are used in applications with large input voltages, care should be exercised to avoid exceeding these devices maximum internal power dissipation. exceeding the published specifications for maximum power dissipation or junction temperature could result in premature device failure. the following formula should be used to calculate a devices maximum junction temperature or dissipation: p d = t j t a q ja in this equation, t j and t a are the junction and ambient tem- peratures, respectively, p d is the device power dissipation and q ja is the device package thermal resistance.
ref19x series C18C rev. d membrane switch controlled power supply with output load currents in the tens of ma, the ref19x family of references can operate as a low dropout power supply in hand-held instrument applications. in the circuit shown in figure 16, a membrane on/off switch is used to control the operation of the reference. during an initial power-on condi- tion, the sleep pin is held to gnd by the 10 k w resistor. recall that this condition disables (read: three-state) the ref19x output. when the membrane on switch is pressed, the sleep pin is momentarily pulled to v in , enabling the ref19x output. at this point, current through the 10 k w is reduced and the internal current source connected to the sleep pin takes control. pin 3 assumes and remains at the same potential as v in . when the membr ane off switch is pressed, the sleep pin is momentar ily connected to gnd, which once again disables the ref19x output. nc nc v in 1 2 3 4 8 7 6 5 nc nc output on off 10k v 1k v 5% ref19x 1 m f tant figure 16. membrane switch controlled power supply current-boosted references with current limiting while the 30 ma rated output current of the ref19x series is higher than typical of other reference ics, it can be boosted to higher levels if desired, with the addition of a simple external pnp transistor, as shown in figure 17. full time current limit- ing is used for protection of the pass transistor against shorts. u1 ref196 (see table) r4 2 v r1 1k v r2 1.5k v q2 2n3906 c2 100 m f/25v d1 1n4148 (see text on sleep) r3 1.82k v c1 10 m f/25v (tantalum) s f c3 0.1 m f f s r1 q1 tip32a (see text) +v s = 6 to 9v (see text) v s common v c v out common output table u1 ref192 ref193 ref196 ref194 ref195 v out (v) 2.5 3.0 3.3 4.5 5.0 +v out 3.3v @ 150ma figure 17. a boosted 3.3 v reference with current limiting in this circuit, the power supply current of reference u1 flowing through r1Cr2 develops a base drive for q1, whose collector provides the bulk of the output current. with a typical gain of 100 in q1 for 100 maC200 ma loads, u1 is never required to furnish more than a few ma, so this factor minimizes tempera- ture related drift. short circuit protection is provided by q2, which clamps drive to q1 at about 300 ma of load current with values as shown. with this separation of control and power functions, dc stability is optimum, allowing best advantage use of premium grade ref19x devices for u1. of course, load management should still be exercised. a short, heavy, low dcr (dc resistance) conductor should be used from u1C6 to the v out sense point s, where the collector of q1 connects to the load, point f. because of the current limiting configuration, the dropout volt- age circuit is raised about 1.1 v over that of the ref19x de- vices, due to the v be of q1 and the drop across current sense resistor r4. however, overall dropout is typically still low enough to allow operation of a 5 v to 3.3 v regulator/reference using the ref196 for u1 as noted, with a v s as low as 4.5 v and a load current of 150 ma. the requirement for a heat sink on q1 depends on the maxi- mum input voltage and short circuit current. with v s = 5 v and a 300 ma current limit, the worst case dissipation of q1 is 1.5 w, less than the to-220 package 2 w limit. however, if smaller to-39 or to-5 packaged devices such as the 2n4033 are used, the current limit should be reduced to keep maximum dissipation below the package rating. this is accomplished by simply raising r 4. a tantalum output capacitor is used at c1 for its low esr (equivalent series resistance), and the higher value is required for stability. capacitor c2 provides input bypassing and can be an ordinary electrolytic. shutdown control of the booster stage is shown as an option, and when used some cautions are in order. because of the additional active devices in the v s line to u1, direct drive to pin 3 does not work as with an unbuffered ref19x device. to enable shutdown control, the connection to u1-2 is broken at the x, and diode d1 then allows a cmos control source v c to drive u1-3 for on-off operation. startup from shutdown is not as clean under heavy load as it is in basic ref19x series and can require several milliseconds under load. nevertheless, it is still effective and can fully control 150 ma loads. when shutdown control is used, heavy capacitive loads should be minimized.
rev. d C19C ref19x series a negative precision reference without precision resistors in many current-output cmos dac applications, where the output signal voltage must be of the same polarity as the reference voltage, it is often required to reconfigure a cur- rent-sw itching dac into a voltage-switching dac through the use of a 1.25 v reference, an op amp and a pair of resistors. using a current-switching dac directly requires an additional operational amplifier at the output to reinvert the signal. a negative voltage reference is then desirable from the point that an additional operational amplifier is not required for either reinversion (current-switching mode) or amplification (voltage switching mode) of the dac output voltage. in general, any positive voltage reference can be converted into a negative volt- age reference through the use of an operational amplifier and a pair of matched resistors in an inverting configuration. the disadvantage to that approach is that the largest single source of error in the circuit is the relative matching of the resistors used. the circuit illustrated in figure 18 avoids the need for tightly matched resistors with the use of an active integrator circuit. in this circuit, the output of the voltage reference provides the input drive for the integrator. the integrator, to maintain cir- cuit equilibrium, adjusts its output to establish the proper rela- tionship between the references v out and gnd. thus, any desired negative output voltage can be chosen by sim ply sub- stituting for the appropriate reference ic. the sleep feature is maintained in the circuit with the simple addition of a pnp transistor and a 10 k w resistor. one caveat with this approach should be mentioned: although rail-to-rail output amplifiers work best in the application, these operational amplifiers require a finite amount (mv) of headroom when required to provide any load current. the choice for the circuits negative supply should take this issue into account. a1 +5v C5v 100 v 1 m f 1k v 1 m f Cv ref 100k v ref19x v in gnd v ref sleep 10k v sleep ttl/cmos a1 = 1/2 op295, 1/2 op291 v in 10k v 2n3906 figure 18. a negative precision voltage reference uses no precision resistors stacking reference ics for arbitrary outputs some applications may require two reference voltage sources that are a combined sum of standard outputs. the circuit of figure 19 shows how this stacked output reference can be implemented. u2 ref19x (see table) r1 3.9k v (see text) c1 0.1 m f +v s v s > v out2 +0.15v v in common v out common output table u1/u2 ref192/ref192 ref192/ref194 ref192/ref195 v out1 (v) 2.5 2.5 2.5 v out2 (v) 5.0 7.0 7.5 +v out2 v o (u2) c2 1 m f c3 0.1 m f +v out1 v o (u1) c4 1 m f u1 ref19x (see table) figure 19. stacking voltage references with the ref19x two reference ics are used, fed from a common unregulated input, v s . the outputs of the individual ics are simply con- nected in series as shown, which provides two output voltages, v out1 and v out2 . v out1 is the terminal voltage of u1, while v out2 is the sum of this voltage and the terminal voltage of u2. u1 and u2 are simply chosen for the two voltages that supply the required outputs (see table). if, for example, both u1 and u2 are ref192s, the two outputs are 2.5 v and 5.0 v. while this concept is simple, some cautions are in order. since the lower reference circuit must sink a small bias current from u2 (50 m aC100 m a), plus the base current from the series pnp output transistor in u2, either the external load of u1 or r1 must provide a path for this current. if the u1 minimum load is not well defined, resistor r1 should be used, set to a value that will conservatively pass 600 m a of current with the applicable v out1 across it. note that the two u1 and u2 reference circuits are locally treated as macrocells, each having its own bypasses at input and output for best stability. both u1 and u2 in this circuit can source dc currents up to their full rating. the mini- mum input voltage, v s , is determined by the sum of the out- puts, v out2 , plus the dropout voltage of u2. a related variation on stacking two three-terminal references is shown in figure 19, where u1, a ref192, is stacked with a two-terminal reference diode such as the ad589. like the three-terminal stacked reference above, this circuit provides two outputs, v out1 and v out2 , which are the individual terminal voltages of d1 and u1 respectively. here this is 1.235 and 2.5, which provides a v out2 of 3.735 v. when using two-terminal reference diodes such as d1, the rated minimum and maximum device currents must be observed and the maximum load cur- rent from v out1 can be no greater than the current set up by r1 and v o(u1) . in the case with v o(u1) equal to 2.5 v, r1 provides a 500 m a bias to d1, so the maximum load current available at v out1 is 450 m a or less.
ref19x series C20C rev. d switched output 5 v/3.3 v reference applications often require digital control of reference voltages, selecting between one stable voltage and a second. with the sleep feature inherent to the ref19x series, switched output reference configurations are easily implemented with relatively little additional hardware. the circuit of figure 22 illustrates the general technique, which takes advantage of the output wire-or capability of the ref19x device family. when off, a ref19x device is effec- tively an open circuit at the output node with respect to the power supply. when on, a ref19x device can source current up to its current rating, but sink only a few m a (essentially just the relatively low current of the internal output scaling divider). as a result, for two devices wired together at their common outputs, the output voltage is simply that of the on device. the off state device will draw a small standby current of 15 m a (max), but otherwise will not interfere with operation of the on device, which can operate to its full current rating. note that the two dev ices in the circuit conveniently share both input and output capacitors, and with cmos logic drive, it is power efficient. using dissimilar ref19x series devices with this configuration allows logic selection between the u1/u2 specified terminal voltages. for example, with u1 (a ref195) and u2 (a ref196), as noted in the table, changing the cmos compatible v c logic control voltage from hi to lo selects between a nominal output of 5.000 v and 3.300 v and vice versa. other ref19x family units can also be used for u1/u2, with similar operation in a logic sense, but with outputs as per the individual paired devices (see table, again). of course, the exact output voltage tolerance, drift and overall quality of the reference voltage will be consis- tent with the grade of individual u1 and u2 devices. u1 ref19x (see table) c1 0.1 m f +v s = 6v v in common v out common +v out c2 1 m f u2 ref19x (see table) 3 4 1 2 u3b 74hc04 u3a 74hc04 v c output table v out (v) 5.0 3.3 4.5 5.0 v c * hi lo hi lo u1/u2 ref195/ ref196 ref194/ ref195 * cmos logic levels figure 22. switched output reference u1 ref192 r1 4.99k v (see text) c1 0.1 m f +v s v s > v out2 +0.15v v in common v out common +v out2 3.735v v o (u1) c2 1 m f d1 ad589 v o (d1) c3 1 m f +v out1 1.235v figure 20. stacking voltage references with the ref19x a precision current source many times, in low power applications, the need arises for a precision current source that can operate on low supply volt- ages. as shown in figure 21, any one of the devices in the ref19x family of references can be configured as a precision current source. the circuit configuration illustrated is a floating current source with a grounded load. the references output voltage is bootstrapped across r set , which sets the output cur- rent into the load. with this configuration, circuit precision is maintained for load currents in the range from the references supply current (typically, 30 m a) to approximately 30 ma. the low dropout voltage of these devices maximizes the current sources output voltage compliance without excess headroom. 1 m f ref19x v in gnd v ref sleep v in i sy adjust r1 p1 r l r set i out v in i out ? r l (max) + v sy (min) i out = + i sy (ref19x) r set v out r set v out >> i sy e.g. ref195 : v out = 5v i out = 5ma r1 = 953 v p1 = 100 v , 10-turn figure 21. a low dropout, precision current source the circuits governing equations are: v in = i out r l ( max ) + v sy ( min , ref 19 x ) i out = v out r set + i sy ( ref 19 x ) v out r set ?? i sy ( ref 19 x )
rev. d C21C ref19x series resistance within the forcing loop of the op amp. since the op amp senses the load voltage, op amp loop control forces the output to compensate for the wiring error and to produce the correct voltage at the load. depending on the reference device chosen, operational amplifiers that can be used in this applica- tion are the op295, the op291 and the op183/op283. 1 m f ref19x v in gnd v out v in 100k v r l r lw sleep v in 2 3 1 a1 r lw +v out sense +v out force a1 = 1/2 op295 1/2 op292 1/2 op283 figure 23. a low dropout, kelvin connected voltage reference a fail-safe 5 v reference some critical applications require a reference voltage to be maintained constant, even with a loss of primary power. the low standby power of the ref19x series and the switched out- put capability allow a fail-safe reference configuration to be implemented rather easily. this reference maintains a tight output voltage tolerance for either a primary power source (ac line derived) or a standby (battery derived) power source, auto- matically switching between the two as the power conditions change. the circuit in figure 24 illustrates the concept, which borrows from the switched output idea of figure 21, again using the ref19x device family output wire-or capability. in this case, since a constant 5 v reference voltage is desired for all there is one application caveat that should be understood about this circuit, which comes about due to the wire-or nature. since u1 and u2 can only source current effectively, negative going output voltage changes, which require the sinking of cur- rent, will necessarily take longer than positive going changes. in practice, this means that the circuit is quite fast when undergo- ing a transition from 3.3 to 5 v, but the transition from 5 to 3.3 v will take longer. exactly how much longer will be a func- tion of the load r esistance, r l , seen at the output and the typi cal 1 m f value of c2. in general, a conservative transition time here will be on the order of several milliseconds for load resistances in the range of 100 w C1 k w . note that for highest accuracy at the new output voltage, several time constants should be allowed (>7.6 time constants for <1/2 lsb error @ 10 bits, for example). kelvin connections in many portable instrumentation applications where pc board cost and area go hand-in-hand, circuit interconnects are very often of dimensionally minimum width. these narrow lines can cause large voltage drops if the voltage reference is required to provide load currents to various functions. in fact, a circuits interconnects can exhibit a typical line resistance of 0.45 m w / square (1 oz. cu, for example). in those applications where these devices are configured as low dropout voltage regulators, these wiring voltage drops can become a large source of error. to circumvent this problem, force and sense connections can be made to the reference through the use of an operational ampli- fier, as shown in figure 23. this method provides a means by which the effects of wiring resistance voltage drops can be elimi- nated. load currents flowing through wiring resistance produce an i-r error (i load r wire ) at the load. however, the kelvin connection overcomes the problem by including the wiring u1 ref195 c1 0.1 m f v s , v bat common v out common +5.000v c3 1 m f u2 ref195 r5 100k v r6 100 v c2 0.1 m f 6 4 2 3 u3 ad820 r4 900k v c4 0.1 m f r2 100k v r3 10m v r1 1.1m v +v bat +v s q1 2n3904 7 figure 24. a fail-safe 5 v reference
ref19x series C22C rev. d conditions, two ref195 devices are used for u1 and u2, with their on/off switching controlled by the presence or absence of the primary dc supply source, v s . v bat is a 6 v battery backup source that supplies power to the load only when v s fails. for normal (v s present) power conditions, v bat sees only the 15 m a (max) standby current drain of u1 in its off state. in operation, it is assumed that for all conditions either u1 or u2 is on and a 5 v reference output is available. with this voltage constant, a scaled down version is applied to the com- parator ic u3, providing a fixed 0.5 v input to the (C) input for all power conditions. the r1Cr2 divider provides a signal to the u3 (+) input proportional to v s , which switches u3 and u1/u2 dependent upon the absolute level of v s . op amp u3 is configured here as a comparator with hysteresis, which provides for clean, noise free output switching. this hysteresis is impor- tant to eliminate rapid switching at the threshold due to v s ripple. further, the device chosen is the ad820, a rail-rail output device, which provides hi and lo output states within a few mv of v s and ground for accurate thresholds and compat- ible drive for u2 for all v s conditions. r3 provides positive feedback for circuit hysteresis, changing the threshold at the (+) input as a function of u3s output. for v s levels lower than the lower threshold, u3s output is low, thus u2 and q1 are off, while u1 is on. for v s levels higher than the upper threshold, the situation reverses, with u1 off and both u2 and q1 on. in the interest of battery power conservation, all of the comparison switching circuitry is powered from v s and is so arranged that when v s fails the de- fault output comes from u1. for the r1Cr3 values as shown, the lower/upper v s switching thresholds are approximately 5.5 v and 6 v, respec- tively. these can obviously be changed to suit other v s sup- plies, as can the ref19x devices used for u1 and u2, over a range of 2.5 v to 5 v of output. u3 can operate down to a v s of 3.3 v, which is generally compatible with all family devices. a low power, strain gage circuit as shown in figure 25, the ref19x family of references can be used in conjunction with low supply voltage operational amplifiers, such as the op492 and the op283, in a self-con- tained strain gage circuit. in this circuit, the ref195 was used as the core of this low power, strain gage circuit. other refer- ences can be easily accommodated by changing circuit element values. the references play a dual role as the voltage regulator to provide the supply voltage requirements of the strain gage and the operational amplifiers as well as a precision voltage reference for the current source used to stimulate the bridge. a distinct feature of the circuit is that it can be remotely controlled on or off by digital means via the sleep pin. 500 v 0.1% 57k v 1% 0.1 m f 10k v 1% 0.1 m f 1/4 op492 10 m f 1 m f ref195 1/4 op492 1/4 op492 1/4 op492 2.21k v 20k v 1% 10k v 1% 20k v 1% 20k v 1% 0.01 m f 10 m f 100 v output 2n2222 20k v 1% 10k v 1% figure 25. a low power, strain gage circuit
rev. d C23C ref19x series outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (p suffix) (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead narrow body so (s suffix) (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead tssop (ru suffix) (ru-8) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.0256 (0.65) bsc seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 printed in u.s.a. c1951dC2C3/99

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